1. Field of the Invention
This invention relates to a collector dot AND circuit. and more particularly to a collector dot AND circuit suitable for use to construct a multi-output AND circuit.
2. Description of the Prior Art
A collector dot AND circuit in which a latched comparator circuit is incorporated is conventionally employed in various technical fields such as, for example a field of logic circuits. An exemplary one of conventional collector dot circuits is shown in FIG. 2. Referring to FIG. 2, the collector dot circuit shown includes a first differential circuit 30 constituted from a pair of transistors Q2 and Q8, and a second differential circuit 31 constituted from another pair of transistors Q10 and Q16. Electric currents flowing through a pair of constant-current sources 32 and 33 are supplied to the first and second differential circuits 30 and 31 by way of a pair of transistors Q4 and Q12, respectively.
A reference signal is supplied to the base of the transistor Q2 constituting the first differential circuit 30 while an analog input signal A1 is supplied to the base of the other transistor Q8. Similarly, another reference signal is supplied to the base of the transistor Q10 constituting the second differential circuit 31 while another analog signal A2 is supplied to the base of the other transistor Q16.
The collector of the transistor Q2 is connected to a power source Vcc by way of a resistor R1, a transistor Q1 and another resistor R2, and an AND output signal B1 is obtained from a junction between the transistor Q1 and the resistor R2.
A resistor R3 and a transistor Q7 are connected to the collector of the transistor Q8 while another resistor R5 and another transistor Q9 are connected to the collector of the transistor Q10. The collectors of the transistors Q7 and Q9 are connected commonly, and an AND output signal B2 is obtained from a junction between the collectors of the transistors Q7 and Q9. The commonly connected collectors of the transistors Q7 and Q9 are connected to the power source Vcc by way of a resistor R4.
The collector of the transistor Q16 is connected to the power source Vcc by way of a resistor R6, a transistor Q15 and another resistor R7, and an output is extracted from a junction between the transistor Q15 and the resistor R7 and is supplied to a differential circuit at a next stage.
A latch circuit 34 constituted from a pair of transistors Q3 and Q6 for effecting a latching operation is connected to the first differential circuit 30 having such construction as described above, and an electric current flowing through the constant-current source 32 is supplied to the latch circuit 34 by way of a transistor Q5. Meanwhile, another latch circuit 35 constituted from a pair of transistors Q11 and Q14 is connected to the second differential circuit 31, and an electric current flowing through the constant-current source 33 is supplied to the latch circuit 35 by way of a transistor Q13.
In the conventional collector dot AND circuit of FIG. 2 having such construction as described above, when an inverted clock signal CLK presents a high ("H") level, the transistors Q4 and Q12 present an on state, and consequently, comparison between a reference signal and an input analog signal is performed with each of the first and second differential circuits 30 and 31. On the contrary when a clock signal CLK presents an "H" level, the transistors Q5 and Q13 present an on state, and consequently, latching of the comparator is performed.
Thus, an AND output corresponding to two analog input signals Al and A2 is obtained from the collectors of the transistors Q7 and Q9 which are connected commonly and connected to the power source by way of the pull-up resistor R4.
In this manner, conventional collector dot AND circuits are constructed such that the collectors of transistors which constitute a pair of adjacent differential circuits are connected commonly and an AND output signal is obtained from the thus commonly connected collectors of the transistors. Accordingly, an analog to digital converter having such a construction as shown, for example, in FIG. 3 cannot be constructed using a collector dot AND circuit.
In particular, referring to FIG. 3, the analog to digital converter shown includes a resistor set 40 including cascade connected resistors PR1 to PR16, a comparator block 41 for comparing voltages of adjacent ones of the resistors PR1 to PR16, a higher order bit controlling AND gate block 42, a lower order bit controlling AND gate block 43, a higher order bit encoder 44, a lower order bit encoder 45 and so forth. The analog to digital converter thus outputs, from digital signal output terminals D1 (MSB) to D4 (LSB) thereof, digital signals corresponding to input analog signals A1 to A15.
The analog to digital converter produces AND output signals B1 to B15 using a plurality of AND gates. And, as apparently seen from FIG. 3, the AND output signals B8 and B12 are formed not from two adjacent circuits but from two circuits provided in a spaced relationship by four circuit distances from each other. Accordingly, if it is tried to construct such a circuit as shown in FIG. 3 using a conventional collector dot AND circuit, additional gates are required as much which makes the scale of the entire circuitry large. Further, if the number of gates increases, then a delay of a signal is increased and the power consumption is increased.